- Engineer will be involved in new and existing ASIC projects working in teams.
- The team is currently working on a mix of IP design/verification and different level of SubSys integration/verification.
- At least 3 years of experience in UVM.
- Good command on UVM verification and System Verilog.
- Should have worked with complex ASIC and/or large FPGA design.
- Experience from IP block verification, Multi clock domains, RTL within Verilog, VHDL and/or System Verilog.
- Meritorious in Test bench structuring and design, RTL design.
- Scripting skills, Lab experience, Telecommunication experience is essential.
- Responsible and self-organized
- Able to prioritize the workload/tasks
- Quick learner and not afraid to face technical challenges
- Social and hold good team skills
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Beskrivning
We are hiring for multiple ASIC Verification Engineer to join a team that develops complex designs based in Sweden.
Educational Qualification: Bachelor of Engineering/M.Sc in Engineering or Equivalent.
Job Summary:
Required Experience / Competences:
Job Features
Job Category Hardware
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