- Engineers will be involved in RTL design of different blocks including Static timing analysis and Block design.
- 5+ years of experience as FPGA Designer.
- Experience in VHDL/Verilog/System Verilog is a strong merit.
- Experience in Test Bench development with UVM will be good to have.
- Must have experience in Xilinx and/or Intel platform and Tools (Vivado, Quartus).
- Knowledge on Timing Analysis.
- Experience in TCL, Python, Perl is a merit.
- Experience in Telecom Radio products, Ethernet communication is a merit.
- Experience / knowledge in Embedded Systems Development projects is a merit.
- Experience working Lab environment will be advantageous.
- Excellent communication in English skills.
- Can do attitude together with strong quality focus.
- Strong in analytical thinking.
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Beskrivning
We are hiring for multiple FPGA Design Engineers for the position based in Sweden.
Educational Qualification: Bachelors or Masters in Engineering or equivalent.
Job Summary:
Required Experience / Competences:
Soft Skills:
Job Features
Job Category Hardware
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